The node is not a number anymore

Ask anyone outside the industry what a chip is, and they will reach for a number. Three nanometres. Two. Soon, if you believe the press releases, one-point-six. The number is supposed to be a measurement, the width of something small enough to be heroic, and for forty years it more or less was. It is not anymore. There is no feature on a modern leading-edge transistor that is sixteen angstroms wide. The name TSMC has given its newest process, A16, refers to nothing you could put a ruler to. It is a marketing label for a generation, and the generation it labels is not a smaller transistor. It is a different kind of object entirely.

This matters more than it sounds. For most of computing's history you could read a single number off a fab's roadmap and infer almost everything you cared about — how fast, how dense, how cheap, how soon. The number did the work. That era is over, quietly, without an announcement, and the people who still read the roadmap the old way are misreading it. The performance that used to live inside the transistor has migrated outward, into how the power gets in, how the dies are joined, how the heat gets out. The node is no longer where the gains are. The node is just the part of the system that still has a famous name.

Power from the back

Begin with the most physical change, the one you can almost feel. For the entire history of the integrated circuit, a chip has been wired from one side. Signal and power both arrived through the same dense stack of copper laid over the transistors, dozens of layers thick, and as transistors shrank, the wires fighting for that space grew more crowded and more resistant. The power network, in particular, became a tax — voltage lost as heat before it ever reached the logic that needed it. You were starving the front of the chip to feed it.

A16 is the first TSMC process built around the obvious-once-you-say-it fix: turn the wafer over and deliver power from the back. TSMC calls its version Super Power Rail, and what makes it more than a relocation is that it does not merely route power along the back of the die — it connects the backside network directly to each transistor's source and drain through a dedicated contact, rather than threading it down through the signal layers. The wires get shorter, the resistance falls, and the front of the chip is freed up for the signal routing it was always meant to carry. The benefit TSMC quotes is roughly eight to ten per cent more speed at the same power, or about twenty per cent less power at the same speed, against its own 2-nanometre-class N2 process. Those are not transistor numbers. They are plumbing numbers.

The performance that used to live inside the transistor has migrated outward — into how the power gets in, how the dies are joined, how the heat gets out.

Read the fine print and the framing shifts again. A16, originally promised for volume production by the end of 2026, has slipped: at its 2026 technology symposium TSMC laid out a roadmap that pushes A16 into 2027, threads new variants — N2U, and the further-out A14, A13 and A12 — through the years to 2029, and pointedly declines, for now, to commit to the High-NA EUV lithography machines that were once assumed to be the next inevitable step. The single most expensive tool in the building, and the leading-edge foundry is in no hurry to buy it. That alone should tell you the gains are being found elsewhere.

The wafer as a circuit board

Walk the gains downstream and you arrive at packaging, the part of the process that for decades was treated as the boring bit at the end — dice the wafer, glue the chip to a substrate, solder it down. That is not what packaging is now. At the leading edge it is where the system is actually built, and TSMC's name for the family is 3DFabric: CoWoS, which mounts logic dies and stacks of high-bandwidth memory side by side on a single silicon interposer; and SoIC, which bonds dies directly on top of one another, copper to copper, with no solder bumps in between.

The numbers here have become the ones worth watching. TSMC is now in volume production of a CoWoS package five-and-a-half times the size of the largest pattern a lithography machine can print in one exposure — its reticle limit — at yields the company says exceed 98 per cent. It has laid out a path to fourteen-reticle packages by 2028, large enough to carry on the order of ten compute dies and twenty stacks of memory on one slab, and beyond that to System-on-Wafer, where the package stops pretending to be a chip and becomes, frankly, the wafer. An Nvidia accelerator is no longer a chip in any meaningful sense. It is a small circuit board built at fab tolerances, and the interposer it sits on is the real product.

This is why capacity, not feature size, is the constraint everyone in Taiwan now talks about. TSMC projects its advanced-packaging capacity for CoWoS and SoIC growing by more than eighty per cent a year through 2027, and it is still not enough; reporting through this spring has described clients pushed toward rival packaging houses because the queue at the leading edge is full. The bottleneck in the AI build-out has moved. It is no longer the transistor. It is the assembly.

What the number stopped measuring

There is a name for what is happening, and the engineers have been using it for a few years now: system-technology co-optimization. STCO, if you must. The idea is that you can no longer optimise the transistor in isolation and expect the rest to follow, because the rest is now where most of the difficulty lives. Architecture, packaging, power delivery, the thermal and mechanical behaviour of a stack of dies pressed together — all of it has to be co-designed from the start, because each one constrains the others. The transistor is a participant in the system now, not its sovereign.

You can see the logic by following the heat, which is where every one of these advances eventually collides with physics. Stacking dies multiplies the power packed into a given volume and traps the hottest logic in tiers far from the heat sink. Backside power delivery, for all its elegance, puts the power network on the side of the die you also want to cool. The interconnects that carry data between stacked dies have grown so dense that the conventional solder microbumps are giving way to direct copper-to-copper hybrid bonding, and even copper itself is running into a wall — which is why co-packaged optics, light carried into the package on fibre, has stopped being a research curiosity and started appearing on roadmaps. Every gain in integration buys a new problem in thermals or interconnect. The system is a negotiation, and the node is one clause in it.

A modern AI accelerator is not a chip. It is a small circuit board built at fab tolerances — and the interposer it sits on is the real product.

The machines that make the machines, in Arizona

Geography makes the point concrete. When the United States set out to bring leading-edge manufacturing home, it built fabs — TSMC's Arizona plants, the subject of a $165 billion commitment, are running, and the first of them turned a reported $514 million profit in its opening stretch. But a fab that only fabricates wafers ships them back across the Pacific to be packaged, because until now the assembly — the part that turns a wafer into a system — lived almost entirely in Taiwan. A chip made in Arizona was still finished in Taiwan. The dependency had simply moved one link down the chain, to the place no one was looking.

Which is why the genuinely significant thing in TSMC's American expansion is not the third fab. It is the two advanced-packaging facilities, AP1 and AP2, due to break ground this year, the first built to do CoWoS and SoIC on American soil. Only with those does the country have a complete leading-edge chip — front and back, lithography and assembly — without the wafer ever leaving. The fab was always the famous part. The packaging plant is the part that closes the loop, and it is the part that tells you where the value, and the vulnerability, has migrated.

So the next time a foundry announces a node and the headlines reduce it to a number, treat the number as a label on a box and ask what is in the box. Ask where the power enters. Ask how the dies are joined and how many, ask what the package is made of and how large it can grow before it cooks itself, ask whether the plant that assembles it sits on the same island as the plant that printed it. The number used to contain all of that. It does not anymore. It is the name we kept out of habit for a thing that has quietly become something else — and the gap between the name and the thing is exactly where, these days, the whole industry is being decided.