The bottleneck is not the chip

The most contested object in the artificial-intelligence economy is not a chip. It is a slab. A round disc of silicon roughly the size of a dinner plate, polished to a flatness measured in atoms, onto which a machine in a fab on the west coast of Taiwan lowers a finished logic die and a row of memory stacks and bonds them together so precisely that, electrically, they begin to behave as one thing. The process is called CoWoS — Chip on Wafer on Substrate — and it is unglamorous, slow, and almost entirely the reason that some of the most powerful companies on earth spent the spring of 2026 standing in a queue.

We have been trained to read the AI story off the front of the box: the transistor, the node, the number of nanometres, the logo of the firm that designed the part. That is the story the industry is comfortable telling, because it is a story about cleverness. The quieter story is about throughput — about how many of these objects can physically be assembled in a given week, in a given building, by a given company — and it leads, as the upstream stories always do, to a chokepoint that almost no one outside the trade had heard of two years ago.

What the package actually does

To understand why packaging became the constraint, you have to put down the schematic and pick up the physical part. A modern AI accelerator is not a single piece of silicon. It is a compute die — the logic, the thing that does the arithmetic — sitting beside a cluster of high-bandwidth memory, the HBM stacks, each one itself a tower of eight to twelve DRAM dies bonded vertically through holes drilled in the silicon, called through-silicon vias. The hard problem is not making any one of those parts. It is getting them to talk to each other fast enough that the compute die is never left waiting on data, because a starved processor is an expensive heater.

CoWoS solves this by laying the dies side by side on a silicon interposer — a base layer that carries wiring far finer than any ordinary circuit board can, with metal lines a few microns apart — and then mounting that whole assembly onto a package substrate beneath. "When we introduce CoWoS, we are able to bring the HBM memory right beside the compute in a very efficient way," a TSMC executive named Rousseau explained to CNBC in April, describing a newer variant that stacks the parts vertically so they "can really behave as if they're one chip." That sentence is the entire AI hardware boom compressed into a clause. Behaving as if they're one chip is the product. The transistor is just an ingredient.

None of this is fast. A wafer can spend months moving through the packaging flow, and the leading variant — CoWoS-L, which uses small silicon bridges to stitch together dies across an area many times larger than a single lithography exposure can cover — is the most demanding of all. The interposers are growing into objects that strain the imagination of anyone who still pictures a chip as a fingernail. TSMC's own roadmap, presented at its North America Technology Symposium, lays out a 9.5-reticle interposer by 2027 and a 14-reticle package later in the decade — a piece of engineered silicon around 12,000 square millimetres, slightly larger than a CD, carrying twenty compute chiplets and twenty memory modules. The plate is getting bigger. The number of plants that can make it is not.

The slab is rationed

Here is the constraint stated plainly. Global demand for CoWoS capacity, measured the way the trade measures it — in equivalent wafers — has gone from roughly 370,000 wafers in 2024 to around 670,000 in 2025 to an estimated one million in 2026. Demand has, in other words, nearly tripled in two years. And the supply that meets it is concentrated to a degree the industry prefers to discuss in private: TSMC is by a wide margin the dominant supplier of leading-edge advanced packaging, and within TSMC's lines, one customer has done the obvious thing a customer does when it sees a chokepoint coming.

Nvidia has locked up more than half of TSMC's CoWoS capacity through 2027. Industry estimates put its share of the most advanced packaging lines at around 60 percent, with bookings in the range of 800,000 to 850,000 wafers reserved for 2026 alone. This is not a chip order. It is a claim staked on a process — on the physical assembly stations themselves, years out — and it leaves everyone else, from AMD to a field of well-funded accelerator startups, bidding over the remainder.

Nvidia did not just buy chips. It bought the assembly line, years in advance — and in doing so it bought time, while its rivals bought a place in the queue.

What makes this more than a procurement footnote is who the queue contains. Google designs its own AI silicon — the TPU — precisely so that it does not have to depend on Nvidia. But independence in design buys you nothing if you arrive at the same single packaging supplier and find the slabs already spoken for. Reporting through the spring indicated that Google, unable to secure sufficient CoWoS capacity, cut its 2026 TPU production target from an original goal of around four million units to roughly three million. A million accelerators, erased not by a design flaw, not by a shortage of cleverness, but by a shortage of the one slow assembly step that everyone forgot to count.

Read that again, because it is the whole argument. A company with effectively unlimited capital, a world-class chip team, and a decade of custom-silicon experience could not build a quarter of the hardware it wanted to build — because the bottleneck was never the chip. It was the package. And the package belongs, for now, to whoever booked the line first.

The firm nobody photographs

Follow the dependency one link further and you arrive somewhere the cameras never go. When the dominant supplier runs out of room, it does not turn customers away; it sub-contracts. TSMC has been pushing portions of the packaging flow — the substrate steps, the so-called on-substrate work — out to the firms that the rest of the world treats as commodity assemblers, chief among them ASE Technology of Kaohsiung. ASE is an OSAT — an outsourced assembly and test house — the kind of company that gets a single line in a teardown and no profile in the business press. It is now one of the more important nodes in the AI supply chain, and the numbers say so.

ASE expects its advanced packaging revenue to roughly double, to about 3.2 billion dollars in 2026, up from an estimated 1.6 billion the year before and just 250 million as recently as 2023 — a line that has gone vertical, driven by AI demand and by the overflow that TSMC cannot absorb. The company has been raising capital spending to keep pace, building out the floor space and the bonding tools to take work that, two years ago, the world's largest foundry would never have let out of its own buildings. When the chokepoint firm starts handing pieces of its crown jewel to a subcontractor, that is not generosity. It is the sound of a constraint that cannot be relieved any other way fast enough.

Geography, again, is destiny

There is a reason a hardware reporter keeps returning to maps. Almost all of this — the interposers, the bonding, the HBM integration, the firms named and unnamed — happens on or around one seismically active island, in a band of plants within driving distance of each other. The redundancy that any prudent engineer would design into a critical system simply does not exist here. It was never designed out; it was never designed in. The concentration accreted one rational decision at a time, the way chokepoints always do, until the entire planet's supply of frontier AI compute came to rest on a single process step performed in a single small geography by a handful of firms.

Governments have begun to notice the slab, if not always by name. Analysts at CSIS have for some time flagged advanced packaging — and specifically the through-silicon-via tooling that HBM depends on — as a genuine chokepoint in the semiconductor supply chain, a point of leverage as well as a point of fragility. TSMC, for its part, is building its first advanced-packaging facilities in the United States, in Arizona, alongside the fabs it already runs there. "To have that capability right next to the fab in Arizona is going to make their customers very happy," the packaging researcher Jan Vardaman of TechSearch International told CNBC, because it spares the wafers a round trip across the Pacific. A sensible move. Also a slow one. A packaging line is not stood up in a quarter, and the demand curve is not waiting.

How much rides on how little

The temptation, covering AI, is to keep your eyes on the front of the box — the new model, the new accelerator, the benchmark that moved. But the rate at which any of that can actually be built is set further upstream, in a process most people will never see, by a machine lowering a die onto a slab of silicon and bonding it into place with a patience that no amount of capital can hurry. Nvidia understood this and bought the line. Google did not move fast enough and lost a million units. ASE is quietly cashing the difference.

The chip was never the scarce thing. The package is. And the package — the plate-sized interposer, the bonding station, the firm in Kaohsiung you have never heard of, the island you cannot move — is where the whole roaring AI economy narrows to a point. Watch the slab. Everything else is downstream of it.