SK hynix shipped a faster memory chip. The number that matters is the one about heat.

SK hynix said on June 18 that it had shipped samples of its 12-layer HBM4E memory to customers. The headline number is the bandwidth: up to 16 gigabits per second per pin, the fastest the company has shown. That is the figure that will lead most of the coverage, and it is the least interesting thing in the announcement.

The two numbers worth your attention are quieter. The new memory is, the company says, more than 20 percent more power-efficient than the HBM4 generation before it, and its thermal resistance is 17 percent lower. Bandwidth sells the chip. Efficiency and heat decide whether the building it goes into can afford to run.

What HBM actually is, and why it sits next to the bill

High-bandwidth memory is the stack of DRAM that sits beside an AI accelerator and feeds it data. A modern training chip is not bottlenecked by how fast it can do arithmetic; it is bottlenecked by how fast it can be handed the next batch of numbers. HBM is the answer to that problem, and it has become one of the most profitable products in the semiconductor industry precisely because every AI accelerator needs a lot of it, stacked as tall and as fast as the manufacturer can manage without cooking it.

The "without cooking it" clause is the whole engineering problem. You are stacking twelve layers of DRAM into a single 48-gigabyte package, running it at 16 gigabits a second per pin, and bolting it millimetres from a processor that is already one of the hottest things in the rack. Heat is not a side effect here. It is the constraint that sets how tall you can stack, how fast you can run, and how much of the power you pay for turns into work instead of warmth.

So when SK hynix leads with bandwidth but puts a 17 percent thermal-resistance improvement and a 20-percent-plus efficiency gain in the same breath, read the order in reverse. The cooler chip is what lets the fast chip exist at scale. The company credits its Advanced MR-MUF packaging — the molded underfill process that fills the gaps between stacked dies — for moving heat out of the stack. That is unglamorous materials work. It is also the part that matters.

Price the claim: where the 20 percent shows up

Here is the arithmetic that turns a spec sheet into a consequence. An AI data centre's running cost is dominated by electricity, and a large and rising share of that electricity is not the processors — it is memory and the cooling that memory demands. Memory can account for a meaningful fraction of an accelerator's power draw, and every watt that goes into a chip has to be pulled back out by a cooling system that costs power of its own. You pay for the heat twice: once to make it, once to remove it.

A 20 percent efficiency gain on a component that runs every hour of every day, in a facility measured in tens or hundreds of megawatts, is not a rounding error. It is the difference between fitting your accelerators inside a fixed power budget and not. And the power budget is fixed, because — as anyone who has watched a data-centre project wait years for a grid connection knows — the megawatts are the hard part. You cannot conjure a substation. You can only use what you have more efficiently.

Bandwidth sells the chip. Efficiency and heat decide whether the building it goes into can afford to run.

That is the lens that matters for HBM4E. Not "how fast," but "how many accelerators can I power and cool inside the same envelope as last year." A cooler, more efficient stack means more compute per megawatt, and more compute per megawatt is the only number that scales when the grid will not.

This is a sample, not a shipment

The discipline is to read what was actually announced. These are samples shipped to customers — the start of a qualification process, not the start of mass production. Qualification for memory destined for AI accelerators is a long, exacting business: the customer integrates the part, tests it under sustained load, and decides whether it is reliable enough to design into a product that ships in volume. SK hynix says it will work with partners toward mass production "in a timely manner," which is the phrasing companies use when the date is not theirs to set.

The realistic timeline puts HBM4E into shipping AI accelerators from 2027. The next generation of training chips — the parts that will use this memory — are the ones that haven't launched yet. So the right way to file this is as a marker on the cost curve, not a product you can buy power for today. The chip that uses it is still a roadmap.

The race is the point

SK hynix is not alone, and the timing of its announcement says so. Samsung said it shipped its own 12-layer HBM4E samples — also at up to 16 gigabits a second, also touting efficiency gains — in late May, a few weeks ahead. Two suppliers reaching the same milestone within a month of each other is not a coincidence; it is a market where a single customer's qualification decision can move billions of dollars of orders, and neither supplier can afford to be the one that qualified second.

For the buyers — the handful of companies designing the accelerators that will define the next training cycle — a real two-horse race in HBM is the good outcome. It is competitive pressure on price, on supply, and, increasingly, on the efficiency numbers that decide how much of a fixed power budget turns into useful compute. When the binding constraint is electricity, the supplier who saves you the most watts per bit wins, regardless of whose pin clocks fastest.

So note the 16 gigabits, then forget it. The number that will decide whether HBM4E matters is the one about heat — 17 percent less of it to fight, more than 20 percent more efficiency to bank — because that is the number that survives contact with the electricity meter. The fast memory is the headline. The cool memory is the product.